On Thu, May 10, 2007 at 05:07:02PM -0700, William Lee Irwin III wrote:
> I described it as motivated by such, not really correctly handling it.
> I didn't bother analyzing it for correctness. I'm not surprised at all
> that the TLB flush can be missed where it now stands in the patch. I
> wanted to move it to tlb_finish_mmu() all along, along with quicklist
> management of lower levels of hierarchy.
> quicklist_free() with unflushed TLB entries admits speculation through
> the pagetable entries corresponding to the list links. So tlb_finish_mmu()
> is the place to call quicklist_free() on pagetables. This requires
> distinguishing preconstructed pagetables from freed user pages, which
> is not done in include/asm-generic/tlb.h (and core callers may need
> to be adjusted, pending the results of audits).
> To clarify, upper levels of pagetables are indeed cached by x86 TLB's.
> The same kind of deferral of freeing until the TLB is flushed required
> for leaf pagetables is required for the upper levels as well.
Never mind. The present bit ends up unset because all the vaddrs are
page-aligned, and PDPTE entries (which lack present bits) aren't ever
internally updated until explicit reloads. I'm still not wild about it,
but can't be arsed to deal with it unless it actually breaks.
-- wli
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