Hi,
The following is extracted from function gart_iommu_init()
......
/*
* Unmap the IOMMU part of the GART. The alias of the page is
* always mapped with cache enabled and there is no full cache
* coherency across the GART remapping. The unmapping avoids
* automatic prefetches from the CPU allocating cache lines in
* there. All CPU accesses are done via the direct mapping to
* the backing memory. The GART address is only used by PCI
* devices.
*/
clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size);
......
On my AMD-based system, the GART aperture is reserved as:
Mapping aperture over 65536 KB of RAM @ 4000000
After commenting out clear_kernel_mapping() line, the system would
have sync flood and reset from time to time. However when with this
clear_kernel_mapping() line, no system reset happened.
As we know that CPU prefetch never cross the page boundary, in this
case the page boundary is 4M. Aperture starting address is 4000000,
which is aligned with 4M. So I think CPU prefetch can not touch this
range reserved by GART aperture.
My question is: in which cases would CPU prefetch touch the address
range reserved by GART aperture?
Thanks,
Forrest
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