On Sat, 5 May 2007, Eric Dumazet wrote:
> > Then add ___cacheline_aligned_in_smp or specify the alignment in the various
> > other ways that exist. Practice is that most slabs specify
> > SLAB_HWCACHE_ALIGN. So most slabs are cache aligned today.
>
> Yes but this alignement is dynamic, not at compile time.
>
> include/asm-i386/processor.h:739:#define cache_line_size()
> (boot_cpu_data.x86_cache_alignment)
Ahh.. I did not see that before.
> So adding ____cacheline_aligned to 'struct file' for example would be a
> regression for people with PII or PIII
Yuck.
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