Re: [PATCH] [16/35] i386: Add an option for the VIA C7 which sets appropriate L1 cache

Andi Kleen wrote:

From: Simon Arlott <[email protected]>

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
a cache line length of 64 according to
http://www.digit-life.com/articles2/cpu/rmma-via-c7.html.  This patch sets
gcc to -march=686 and select s the correct cache shift.

Signed-off-by: Simon Arlott <[email protected]>
Signed-off-by: Andi Kleen <[email protected]>
Cc: Andi Kleen <[email protected]>
Cc: Dave Jones <[email protected]>
Cc: Alan Cox <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>


Has it been verified in the field that this CPU supports CMOV?

	Jeff



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Follow-Ups:
- Re: [PATCH] [16/35] i386: Add an option for the VIA C7 which sets appropriate L1 cache
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References:
- [PATCH] [0/35] Some x86 2.6.22 candidate patches for review
  - From: Andi Kleen <[email protected]>
- [PATCH] [16/35] i386: Add an option for the VIA C7 which sets appropriate L1 cache
  - From: Andi Kleen <[email protected]>

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