Re: [PATCH] mm: PageLRU can be non-atomic bit operation

> This seems to imply that we need the lock prefix even when updating
> different bits within the same long (not just the same byte). Is this
> interpretation correct?

Yes, that is what I said. The consistency applies to loads/stores
(so e.g. for 128bit SSE2 load/stores too), not bytes.

The current IA32 manuals have a more detailed description of the rules 
in volume 3

-Andi
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• References:
  • [PATCH] mm: PageLRU can be non-atomic bit operation
    • From: Hisashi Hifumi <[email protected]>
  • Re: [PATCH] mm: PageLRU can be non-atomic bit operation
    • From: Andi Kleen <[email protected]>
  • Re: [PATCH] mm: PageLRU can be non-atomic bit operation
    • From: Fernando Luis Vázquez Cao <[email protected]>

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