Keir Fraser <[email protected]> writes:
> On 13/4/07 03:24, "Zachary Amsden" <[email protected]> wrote:
>
> >> You do know that P6 and higher don't do locked bus references as long
> >> as the value is in the cache, right?
> >
> > Yes. Even then, last time I clocked instructions, xchg was still slower
> > than read / write, although I could be misremembering. And it's not
> > totally clear that they will always be in cached state, however, and for
> > SMP, we still want to drop the implicit lock in cases where the
> > processor might not know they are cached exclusive, but we know there
> > are no other racing users. And there are plenty of old processors out
> > there to still make it worthwhile.
>
> LOCKed instruction suck really badly on the netburst microarchitecture (like
> factor of 10x, or not far off). I think it's probably because of their side
> effect of serialising memory accesses, causing horrible pipeline stalls.
Unfortunately they tend to be HyperThreaded usually (except for early ones
and Celerons) and need the LOCK anyways.
-Andi
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