On Mon, Feb 19, 2007 at 12:37:00PM -0800, Michael K. Edwards wrote:
> What we've seen on our embedded ARM is that enabling an interrupt that
> is shared between multiple UARTs, at a stage when you have not set up
> all the data structures touched by the ISR and softirq, can have
> horrible consequences, including soft lockups and fandangos on core.
Incorrect. We have:
1. registered an interrupt handler at this point.
2. disabled interrupts (we're under the spin lock)
So, no interrupt will be seen by the CPU since the interrupt is masked.
The test is intentionally designed to be safe from the interrupt
generation point of view.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of:
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