> This is accomplished by allocating a page (or more) of memory which
> is executable and mapped into every threads address space. Also, all
> ISR entry points are modified to detect if the code that was interrupted
> was executing within the ACE page. If it was then the ACE code is
> allowed to complete before the ISR continues. This then provides
> the guarantee of atomic execution.
What if you enter the ISR, pass the point of the check and then another
CPU core hits the ACE space ?
Also how do you handle the case where the code gets stuck in your atomic
pages ?
Alan
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