On Sunday 17 December 2006 00:22, Eric W. Biederman wrote:
> Actually can anyone tell me how try_apic_pin is supposed to work at
> all?
>
> It doesn't appear to be programming the io_apic.
magic:-)
ACPI can't even _describe_ the scenarios being tried by check_timer(),
which is trying to navigate the minefield of all possible undocumented
chipset dependent bugs. (ie, tinkering with the PIT when in IOAPIC mode...)
The chipset vendors can create new bugs in this area
faster than we can fix them, and there is a reason for this.
The public info on Windows says that they use 100HZ IRQ0 8254 only for UP.
On SMP, they use 64 HZ RTC on IRQ8 instead.
This means that for the population of system vendors that validate only with Windows,
only those timers are getting validated, and Linux on IRQ0 is exposed to HW bugs.
So the RTC looks like a safe path for a validated periodic ticker
when our first choice doesn't work. But the RTC isn't without problems.
It can tick only in powers of 2 HZ, and 100/250/300/1000 are not powers of 2.
Dunno if close counts -- 256 is close to our 250, and 1024 is close to our 1000,
but we don't have any choices close to 100 or 300 HZ.
-Len
ps.
Moving to the RTC from the PIT would move us 3 years forward
in hardware technology, from 1981 to 1984:-)
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