On Wed, 2006-12-13 at 17:51 +0000, Ben Dooks wrote:
> > > +
> > > + writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
> > > +
> > > + dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
> > > + gate, clock, mode);
> > > +
> > > + msleep(16);
> >
> > you're missing a PCI posting flush here
> > (if you don't know what this is please ask)
>
> Is this a read from an device register to cause the PCI writes
> to happen?
yup
> Would reading SM501_POWER_MODE_CONTROL be ok, or does
> it require a different register?
any register is ok, you can read the same one just fine.
greetings,
Arjan van de Ven
--
if you want to mail me at work (you don't), use arjan (at) linux.intel.com
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