> I'm worried by this... At no point do you check the host bridge
> capabilities, and thus will happily set the max read req size to some
> value larger than the max the host bridge can cope...
Well, it's disabled by default... the option is there as a quick way
to fix "why is my bandwidth so low" when a broken BIOS sets these to
minimum values. Maybe we should just strip out that code and point
people who want to tweak this at setpci instead.
> So for PCI-X, if we want tat, we need a pcibios hook for the platform
> to validate the size requested. For PCI-E, we can use standard code to
> look for the root complex (and bridges on the path to it) and get the
> proper max value.
Actually even PCIe might not be that easy. For example with current
kernels on PowerPC 440SPe (SoC with PCIe), I just get:
# lspci
00:01.0 InfiniBand: Mellanox Technology: Unknown device 6274 (rev a0)
ie no host bridge / root complex.
- R.
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