On Fri, Oct 20, 2006 at 05:38:32PM -0700, Linus Torvalds wrote:
> On Sat, 21 Oct 2006, Ralf Baechle wrote:
> > > That said, maybe nobody does that. Virtual caches are a total braindamage
> > > in the first place, so hopefully they have limited use.
> >
> > On MIPS we never had pure virtual caches.
>
> Ok, so on MIPS my schenario doesn't matter.
>
> I think (but may be mistaken) that ARM _does_ have pure virtual caches
> with a process ID, but people have always ended up flushing them at
> context switch simply because it just causes too much trouble.
Just read this, sorry.
The majority of ARM CPU implementations have pure virtual caches
_without_ process IDs. (Some have a nasty hack which involves
remapping the lower 32MB of virtual memory space to other areas
of the cache's virtual space, but obviously that limits you to
32MB of VM.)
Thankfully, with ARM version 6, they had an inkling of clue, and
decided to move to VIPT caches but with _optional_ aliasing, and
if the CPU design was Harvard there's a possibility for D/I cache
aliasing.
> > Be sure I'm sending a CPU designers a strong message about aliases.
>
> Castration. That's the best solution. We don't want those people
> procreating.
Absolutely. Can we start such a program in Cambridge, England ASAP
please?
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of:
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