Tejun Heo wrote:
In short, some piix controllers including ICH7, when put into enhanced
mode (PCI native mode), uses BMDMA Interrupt bit as interrupt
pending/clear bit for *all* commands. ie. Reading STATUS does NOT clear
Yep. I thought I had mentioned this, ages ago.
Fortunately, libata is immune to the problem because it does
ap->ops->irq_clear(ap) in ata_host_intr() regardless of command type in
flight. So, not loading IDE piix and using libata to drive all piix
ports solves the problem.
Yep, that's intentional :)
Jeff
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