On Oct 30, 2006, at 09:38:00, Arjan van de Ven wrote:
I admit the complexity is a bit high, but since the maximum
nesting is bounded by the complexity of the hardware and the
number of busses, and the maximum memory-allocation is strictly
limited in the single-threaded case this could allow 64-way
systems to probe all their hardware an order of magnitude faster
than today without noticeably impacting an embedded system even in
the absolute worst case.
how much of this complexity goes away if you consider the scanning/
probing as a series of "work elements", and you end up with a queue
of work elements that threads can pull work off one at a time (so
that if one element blocks the others just continue to flow). If
you then find, say, a new PCI bus you just put another work element
to process it at the end of the queue, or you process it
synchronously. Etc etc.
Well, I suppose the "trick" would be to ensure that the top-level
code can probe multiple independent busses in parallel, while
allowing certain of those to serialize their execution order for
whatever reason without changing the resulting linear order. This
would make it possible to have independent pci.multithread_probe=1
and scsi.multithread_probe=1 arguments so the sysadmin can force
serialization for one subsystem if they don't have their device-
numbering issues with that subsystem entirely sorted out.
Cheers,
Kyle Movvett
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