Re: AMD X2 unsynced TSC fix?

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



> Nothing at all, or just the the low few bits are writeable?  I had heard,
> but never seen that some Intel CPUs only allowed 16 bits of writable bits
> in the TSC MSR.  I also heard of, but never saw, CPUs that cleared the TSC
> to 0 on a write!

Normally on Intel you can only write the first 32bits

-Andi

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [email protected]
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[Index of Archives]     [Kernel Newbies]     [Netfilter]     [Bugtraq]     [Photo]     [Stuff]     [Gimp]     [Yosemite News]     [MIPS Linux]     [ARM Linux]     [Linux Security]     [Linux RAID]     [Video 4 Linux]     [Linux for the blind]     [Linux Resources]
  Powered by Linux