Re: Ordering between PCI config space writes and MMIO reads?

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To: Grant Grundler <[email protected]>

Subject: Re: Ordering between PCI config space writes and MMIO reads?

From: Roland Dreier <[email protected]>

Date: Wed, 25 Oct 2006 07:11:06 -0700

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Cc: [email protected], [email protected], [email protected], [email protected], John Partridge <[email protected]>

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In-reply-to: <[email protected]> (Grant Grundler's message of "Wed, 25 Oct 2006 00:30:22 -0600")

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 > I'm looking at arch/ia64/pci/pci.c.
 > Wouldn't it be reasonable to include memory barriers around calls
 > to SAL config space access functions?

It's reasonable, but is there a memory barrier strong enough to
guarantee that a config write has actually completed?

 - R.
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References:
- Ordering between PCI config space writes and MMIO reads?
  - From: Roland Dreier <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
  - From: Grant Grundler <[email protected]>

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