On Fri, 20 Oct 2006, David Miller wrote:
>
> From: Linus Torvalds <[email protected]>
> Date: Fri, 20 Oct 2006 17:38:32 -0700 (PDT)
>
> > I think (but may be mistaken) that ARM _does_ have pure virtual caches
> > with a process ID, but people have always ended up flushing them at
> > context switch simply because it just causes too much trouble.
> >
> > Sparc? VIPT too? Davem?
>
> sun4c is VIVT, but has no SMP variants.
You don't need SMP - we have sleeping sections here, so even threads on UP
can trigger it.
Now, to trigger it you need to have
- virtual indexing not just by address, but by some "address space
identifier" thing too
- (in practice) a big enough cache that switching tasks wouldn't flush it
anyway.
> sun4m has both VIPT and PIPT.
>
> > But it would be good to have something for the early -rc1 sequence for
> > 2.6.20, and maybe the MIPS COW D$ patches are it, if it has performance
> > advantages on MIPS that can also be translated to other virtual cache
> > users..
>
> I think it could help for sun4m highmem configs.
Well, if you can re-create the performance numbers (Ralf - can you send
the full series with the final "remove the now unnecessary flush" to
Davem?), that will make deciding things easier, I think.
I suspect sparc, mips and arm are the main architectures where virtually
indexed caching really matters enough for this to be an issue at all.
Linus
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