Re: [PATCH] i386 add Intel Core related PMU MSRs

[Stephane Eranian <eranian@hpl.hp.com>]

On Wed, Oct 18, 2006 at 02:27:23AM -0700, Stephane Eranian wrote:
> 
> The following patch adds to the i386 tree a bunch of MSRs related to performance
> monitoring for the processors based on Intel Core microarchitecture. It also adds
> some architectural MSRs for PEBS. A similar patch was posted for x86-64.
> 
> changelog:
>         - add Intel Precise-Event Based sampling (PEBS) related MSR
>         - add Intel Data Save (DS) Area related MSR
>         - add Intel Core microarchitecure performance counter MSRs
>
I realized there was a typo for one of the MSR (MSR_CORE_PERF_FIXED_CTR_CTRL).
Here is a resubmit of the same patch. The x86-64 also has the typo. Sorry about that.

changelog:
        - add Intel Precise-Event Based sampling (PEBS) related MSR
        - add Intel Data Save (DS) Area related MSR
        - add Intel Core microarchitecure performance counter MSRs

signed-off-by: stephane eranian <eranian@hpl.hp.com>


diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 62b76cd..1820d9d 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -141,6 +141,10 @@ #define MSR_IA32_MC0_STATUS		0x401
 #define MSR_IA32_MC0_ADDR		0x402
 #define MSR_IA32_MC0_MISC		0x403
 
+#define MSR_IA32_PEBS_ENABLE		0x3f1
+#define MSR_IA32_DS_AREA		0x600
+#define MSR_IA32_PERF_CAPABILITIES	0x345
+
 /* Pentium IV performance counter MSRs */
 #define MSR_P4_BPU_PERFCTR0 		0x300
 #define MSR_P4_BPU_PERFCTR1 		0x301
@@ -284,4 +288,13 @@ #define MSR_TMTA_LONGRUN_FLAGS		0x808680
 #define MSR_TMTA_LRTI_READOUT		0x80868018
 #define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
 
+/* Intel Core-based CPU performance counters */
+#define MSR_CORE_PERF_FIXED_CTR0	0x309
+#define MSR_CORE_PERF_FIXED_CTR1	0x30a
+#define MSR_CORE_PERF_FIXED_CTR2	0x30b
+#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x38d
+#define MSR_CORE_PERF_GLOBAL_STATUS	0x38e
+#define MSR_CORE_PERF_GLOBAL_CTRL	0x38f
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x390
+
 #endif /* __ASM_MSR_H */
-
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