Section 5.3 of PCI Bus Power Management 1.2 states:
There is a minimum recovery time requirement of 200 µs between when
a function is programmed from D2 to D0 and when the function can be
next accessed as a target (including PCI configuration accesses). If
an access is attempted in violation of the specified minimum recovery
time, undefined system behavior may result.
We have to prevent the user running lspci during this time, and
fortunately we already have the pci_block_user_cfg_access() API to
do this.
Signed-off-by: Matthew Wilcox <[email protected]>
---
drivers/pci/pci.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index a544997..1bb059a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -366,6 +366,11 @@ pci_set_power_state(struct pci_dev *dev,
break;
}
+ /* We have to prevent accesses to config space while transitioning
+ * between power states
+ */
+ pci_block_user_cfg_access(dev);
+
/* enter specified state */
pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
@@ -383,6 +388,9 @@ pci_set_power_state(struct pci_dev *dev,
if (platform_pci_set_power_state)
platform_pci_set_power_state(dev, state);
+ /* Should be safe to allow userspace access to the device again now */
+ pci_unblock_user_cfg_access(dev);
+
dev->current_state = state;
/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
--
1.4.1.1
-
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