Andrew Morton <[email protected]> writes:
> On Tue, 26 Sep 2006 20:04:05 -0600
> [email protected] (Eric W. Biederman) wrote:
>
>> When I apply:
>> x86_64-mm-insert-ioapics-and-local-apic-into-resource-map
>>
>> My e1000 fails to initializes and complains about a bad eeprom checksum.
>> I haven't tracked this down to root cause yet and I am in the process of
> building
>> 2.6.18-mm1 with just that patch reverted to confirm that is the only cause.
>>
>> I could not see anything obvious in the patch. I don't have a clue the patch
>> could be triggering the problem I'm seeing.
>>
>> At a quick visual diff I'm not seeing any other differences in the kernel boot
>> logs, or in /proc/iomem.
>
> This bit looks fishy:
>
> GSI 17 sharing vector 0x4A and IRQ 17
> PCI->APIC IRQ transform: 0000:05:0c.0[A] -> IRQ 17
> +PCI: Cannot allocate resource region 8 of bridge 0000:00:02.0
> +PCI: Cannot allocate resource region 8 of bridge 0000:01:00.0
> +PCI: Cannot allocate resource region 8 of bridge 0000:01:00.2
> +PCI: Cannot allocate resource region 0 of device 0000:01:00.1
> +PCI: Cannot allocate resource region 0 of device 0000:01:00.3
> +PCI: Cannot allocate resource region 0 of device 0000:03:04.0
> +PCI: Cannot allocate resource region 0 of device 0000:03:04.1
> PCI-GART: No AMD northbridge found.
> PCI: Bridge: 0000:01:00.0
> IO window: disabled.
> - MEM window: fe000000-fe0fffff
> + MEM window: e2000000-e20fffff
> PREFETCH window: fd000000-fdffffff
> PCI: Bridge: 0000:01:00.2
> IO window: 1000-1fff
> - MEM window: fe100000-fe1fffff
> + MEM window: e2100000-e21fffff
> PREFETCH window: disabled.
> PCI: Bridge: 0000:00:02.0
> IO window: 1000-1fff
> - MEM window: fe000000-fe2fffff
> + MEM window: e2000000-e22fffff
> PREFETCH window: fd000000-fdffffff
> PCI: Bridge: 0000:00:06.0
> IO window: disabled.
> @@ -123,17 +131,17 @@
> PCI: Bridge: 0000:00:1e.0
> IO window: 2000-2fff
> MEM window: fb000000-fc0fffff
> - PREFETCH window: e2000000-e20fffff
>
>
> Wanna hack into arch/i386/pci/i386.c:pcibios_allocate_bus_resources() and
> see what is conflicting with what?
Good catch. Add that to the earlier /proc/iomem output.
> fe200000-fe200fff : IOAPIC 1
> fe201000-fe201fff : IOAPIC 2
On that board I have ioapics on pci devices and it appears the way
the patch is reserving them it doesn't account for ioapics that
have that property. I.e. Those ioapics regions show up in lspci
on an ioapic pci device and the regions are specified with normal
base address registers.
I'm trying to finish up my msi work, so I'm going to avoid further
digging. Hopefully this is enough now that we have a reasonable
explanation someone can actually dig in and fix this problem.
Eric
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