Ar Gwe, 2006-09-15 am 14:34 -0400, ysgrifennodd Frank Ch. Eigler:
> locations, but this is self-modifying code involving multiple
> instructions, and appears to be tricky on SMP/preempt boxes.
Can you explain more about why this is the case. I would have though
that it's the same with one instruction or 100 to the non SMP case. You
may never patch an instruction while another CPU may be executing that
path and there must be a synchronizing point for each CPU before it hits
the patched instruction. See the Intel and AMD chip errata documents.
Figuring out how long to patch is a more complicated problem but there
is extant code to compute the length of an x86 instruction.
Alan
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