Re: Uses for memory barriers

["Paul E. McKenney" <paulmck@us.ibm.com>]

On Tue, Sep 12, 2006 at 05:07:31PM +0200, Oliver Neukum wrote:
> Am Dienstag, 12. September 2006 16:55 schrieb Paul E. McKenney:
> > On Tue, Sep 12, 2006 at 12:22:00PM +0200, Oliver Neukum wrote:
> > > Am Dienstag, 12. September 2006 11:01 schrieb David Howells:
> > > > Paul E. McKenney <paulmck@us.ibm.com> wrote:
> > > > 
> > > > > 2.	All stores to a given single memory location will be perceived
> > > > > 	as having occurred in the same order by all CPUs.
> > > > 
> > > > Does that take into account a CPU combining or discarding coincident memory
> > > > operations?
> > > > 
> > > > For instance, a CPU asked to issue two writes to the same location may discard
> > > > the first if it hasn't done it yet.
> > > 
> > > Does it make sense? If you do:
> > > mov #x, $a
> > > wmb
> > > mov #y, $b
> > > wmb
> > > mov #z, $a
> > > 
> > > The CPU must not discard any write. If you do
> > > 
> > > mov #x, $a
> > > mov #y, $b
> > > wmb
> > > mov #z, $a
> > > 
> > > The first store to $a is superfluous if you have only inter-CPU
> > > issues in mind.
> > 
> > In both cases, the CPU might "discard" the write, if there are no intervening
> > reads or writes to the same location.  The only difference between your
> 
> How can it know that?

If the CPU starts off owning both cache lines, and if there are no intervening
invalidation requests from other CPUs, then the writing CPU knows that there
could not possibly have been any intervening writes.

> > two examples is the ordering of the first store to $a and the store to $b.
> > In your first example, other CPUs must see the first store to $a as happening
> > first, while in your second example, other CPUs might see the store to $b
> > as happening first.
> 
> There's no way in the second case a CPU might tell whether the first
> write ever happened.

With one important exception -- the CPU that did the write knows.
There is no requirement that each and every CPU see each and every write.
The only requirement is that the sequence of values that each CPU sees
for a single given variable is consistent with that of each other CPU.

							Thanx, Paul
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