> Oops, I forgot about store-store ordering being automatic.
> Pretend I had some loads in my example.
Well, in 99% of the cases, you want MMIO loads to be orderd vs. MMIO
stores and thus you can use __writel and __readl (which will only do an
eieio in __readl). If you are really that picky, then, of course you can
go use the __raw_* versions.
> A proper interface would be more explicit about what the
> fence does, so that driver authors shouldn't need to know
> this detail.
What detail ? Isn't my document explicit enough ? If not, please let me
know what is not clear in the definition of the 4 ordering rules and the
matching fences.
> OK, a different discussion... though memory being used
> for DMA seems rather related. You need to flush before
> a DMA out, or invalidate before a DMA in.
This is already documented elsewhere.
> So you say: never mix strict mappings with loose operations,
> and never mix loose mappings with strict operations.
I don't want the concept of "lose mappings" in the generic driver
interface for now anyway :)
It's too implementation specific and I want to know that a given access
is strictly ordered or relaxed just by looking at the accessor used, not
having to go look for where the driver did the ioremap. We can still
provide arch specific things where we feel it's useful but let's move
one step at a time with the generic accessors.
The only "lose" mapping that we'll introduce next is write combining,
but that's also a different debate. Again, one thing at a time :)
> That is an excellent rule. I see no need to stop people from
> actively trying to shoot their feet though. I'm certainly not
> suggesting that people be mixing things.
>
> For some CPUs, you want to be specifying things when you
> set up the mapping. For other CPUs, the read/write code is
> how this gets determined. So developers specify both.
For now, we are assuming that if the mapping controls ordering, then
it's strictly order. We'll see if we hit an arch where that becomes a
problem.
Ben.
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