Re: Uses for memory barriers

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Fri, 8 Sep 2006, Oliver Neukum wrote:

> Am Freitag, 8. September 2006 17:55 schrieb Alan Stern:
> > >     CPU 0                   CPU 1
> > >     -----                   -----
> > >     while (y==0) relax();   y = -1;
> > >     a = 1;                  b = 1;
> > >     mb();                   mb();
> > >     y = b;                  x = a;
> > >                             while (y < 0) relax();
> > >                             assert(x==1 || y==1);   //???
> 
> 					y =  -1
> 	a = 1
> 	y =b (== 0)
> 					b = 1
> 					x = a (==1)

So in this case the assertion is satisfied because x == 1.  My question
was whether the assertion could ever fail.  Paul said that it could, but I
didn't find his reason convincing.

> > Disagree: CPU 0 executes mb() between reading y and b.  You have assumed
> > that CPU 1 executed its write to b and its mb() before CPU 0 got started, 
> > so why wouldn't CPU 0's mb() guarantee that it sees the new value of b?  
> > That's really the key point.
> 
> That code has an ordinary race condition.
> For it to work it needs to be:
> 
> b = 1;
> mb(); //could be wmb()
> y = -1;

I'm not sure what you mean.  The code wasn't intended to "work" in any 
sense; it was just to make a point.  My question still stands: Is it 
possible, in the code as I originally wrote it, for the assertion to fail?

Alan Stern

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [email protected]
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[Index of Archives]     [Kernel Newbies]     [Netfilter]     [Bugtraq]     [Photo]     [Stuff]     [Gimp]     [Yosemite News]     [MIPS Linux]     [ARM Linux]     [Linux Security]     [Linux RAID]     [Video 4 Linux]     [Linux for the blind]     [Linux Resources]
  Powered by Linux