Re: question regarding cacheline size

[Jeff Garzik <jeff@garzik.org>]

Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:53:57PM +0200, Tejun Heo wrote:
> > The spec says that devices can put additional restriction on supported 
> > cacheline size (IIRC, the example was something like power of two >= or 
> > <= certain size) and should ignore (treat as zero) if unsupported value 
> > is written.  So, there might be need for more low level driver 
> > involvement which knows device restrictions, but I don't know whether 
> > such devices exist.
>
> That's nothing we can do anything about.  The system cacheline size is
> what it is.  If the device doesn't support it, we can't fall back to a
> different size, it'll cause data corruption.  So we'll just continue on,
> and devices which live up to the spec will act as if we hadn't
> programmed a cache size.  For devices that don't, we'll have the quirk.
>
> Arguably devices which don't support the real system cacheline size
> would only get data corruption if they used MWI, so we only have to
> prevent them from using MWI; they could use a different cacheline size
> for MRM and MRL without causing data corruption.  But I don't think we
> want to go down that route; do you?

FWIW, there are definitely both ethernet and SATA PCI devices which only 
allow a limited set of values in the cacheline size register... and that 
limited set does not include some of the modern machines.

	Jeff



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