As a temporal work-around to the timeout problem I've put the following in:
1. All data timeout values are multiplied by a fudge factor of 10 (this is still lower latency
than waiting for a software fall-back).
2. I've added a module option to disable hardware data timeout at all. This is how TI does it too
- command timeout is set to 64 clocks are data timeouts (if any) are captured by the slow software
handler. Card removal is signalled by its own interrupt, so the wait for data in this case will be
aborted anyway.
I haven't checked out your patch yet.
For a written blocks I'm now reporting the BUSY de-assert count rather than block counter value. I
hope this is a good idea.
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