Re: [MODSLAB 3/7] A Kmalloc subsystem

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Sat, 19 Aug 2006, Manfred Spraul wrote:

> > And as we have just seen virt to page is mostly an address calculation in
> > many configurations. I doubt that there would be a great advantage. Todays
> > processors biggest cause for latencies are cacheline misses..
> > 
> It involves table walking on discontigmem archs. "slabp=addr &
> (~(PAGE_SIZE-1));" means no pointer chasing, and the access touches the same
> page, i.e. definitively no TLB miss.

There is no table walking for discontigmem on ia64. Ia64 only creates page 
table if it needs to satify the Linux kernels demands for such a thing. 
And this is a kernel mapping. No page table involved.

The current sparsemem approach also does not need table walking. It needs
to do lookups in a table.

UP and SMP currently work cleanly.

> > Power of 2 cache sizes make the object align neatly to cacheline boundaries
> > and make them fit tightly into a page.
> >  
> IMHO not really an issue. 2kb-cache_line_size() also aligns perfectly.

That would work and also be in line with the existing overhead of the 
slabs.




-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [email protected]
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[Index of Archives]     [Kernel Newbies]     [Netfilter]     [Bugtraq]     [Photo]     [Stuff]     [Gimp]     [Yosemite News]     [MIPS Linux]     [ARM Linux]     [Linux Security]     [Linux RAID]     [Video 4 Linux]     [Linux for the blind]     [Linux Resources]
  Powered by Linux