Benjamin Herrenschmidt <[email protected]> writes:
> At this point, the only PPCs with HT interrupts that I know are 970
> based solutions using the Apple U3/U4 bridges (and their IBM
> counterparts). Thus all HT interrupts are routed to the MPIC as sources,
> so things like masking, affinity, etc... are all handled at the MPIC
> level, not at the HT level and they all originate from either an Apple
> home made HT APIC or standard HT APICs in PCI-X/E tunnels. We still need
> to poke around with the HT APICs for configuration and EOI on level
> interrupts (due to a bug in the Apple MPIC, the EOI doesn't get sent
> back to the HT APIC) but we have code locally in the MPIC driver to do
> it and I don't think it would fit well a generic layer.
>
> Things might be different in the future... but for now, I'm afraid I
> have no use of that HT layer.
I didn't really expect you to have an immediate use, but the
confirmation is nice. The interesting part is how I have factored out
the arch specific details. I believe this is close to the direction
you envisioned for msi. If you could look at the basic structure
and confirm that the structure looks properly arch neutral that
would be appreciated. As time permits I want to make the msi code
look more the this hypertransport irq code.
Eric
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