Re: [PATCH 10/17] 2.6.17.1 perfmon2 patch for review: PMU context switch

[Andi Kleen <ak@suse.de>]

> But that is using cpu_clk_unhalted (isn't it?)  If so, it would slow down
> when the system is idle.
> The BIOS writer's guide, Ch. 10.2, says only events outside of the
> processor, 

The other events don't happen by definition. 

If the system is C1 idle there are no cache misses, no pipe line events,
nothing - just cache snoops and waiting for interrupts and TSC
ticking.

> like northbridge DMA accesses, stop counting during halt. 
> (And by definition cpu_clk_unhalted.)

It also depends on which C state and how the BIOS implements your C state.

e.g. there is C1/C2/C3 and then there are various modi of C1
(HLT aka C1 is actually some SMM code in the BIOS that does different
stuff). 
 
I think there is at least one mode that ramps down large parts of the
CPU (it's called C1 clock ramping - that is what has caused the TSC
sync problems on some dual core systems).

I guess your BIOS is not very aggressive in its SMM code in
disabling the CPU.

C2/C3 also depend on SMM code, but when implemented should definitely
stop everything.
 
Intel also has different implementations of C1/C2/C3 depending
on CPU and BIOS. Especially lowend code 

But I still maintain something must be wrong with your 
measurements.

-Andi
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