On Fri, Jun 30, 2006 at 12:10:32PM -0700, Linus Torvalds wrote:
>
>
> On Thu, 22 Jun 2006, Alessio Sangalli wrote:
> >
> > # /sbin/lspci -vvx
> > 00:00.0 Host bridge: Intel Corp. 82440MX Host Bridge (rev 01)
> > Subsystem: Compaq Computer Corporation: Unknown device 000d
> > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> > Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
> > Latency: 64
> > 00: 86 80 94 71 06 00 00 22 01 00 00 06 00 40 80 00
> > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 20: 00 00 00 00 00 00 00 00 00 00 00 00 11 0e 0d 00
> > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> Ok. We don't actually have any quirks at all for the 82440MX, and that's
> almost certainly _not_ because it doesn't do something strange (all Intel
> host bridges have magic IO ranges), but simply because we haven't hit it
> yet.
>
> And I can't find the docs for the PCI config space for that dang thing.
>
> I bet that there's some magic SMBus IO-range that the 440MX decodes using
> a special magic config setting.
>
> Has anybody found the config space docs for the 82440MX?
http://www.codemonkey.org.uk/cruft/440/
There's an assortment of docs for the other flavour Intel PCIsets from
that era in the same dir.
Dave
--
http://www.codemonkey.org.uk
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