the following: "[PATCH] sched: new sched domain for representing
multi-core"
Incorrectly makes SCHED_SMT and some of the structures it uses dependent
on SMP. However, this is wrong, the structures are only defined if
X86_HT, so SCHED_SMT has to depend on that as well.
Signed-off-by: James Bottomley <[email protected]>
---
The patch broke voyager, since it doesn't provide any of the multi-core
or hyperthreading structures.
James
Index: linux-2.6/arch/i386/Kconfig
===================================================================
--- linux-2.6.orig/arch/i386/Kconfig 2006-06-26 10:43:09.000000000 -0500
+++ linux-2.6/arch/i386/Kconfig 2006-06-26 10:52:27.000000000 -0500
@@ -229,7 +229,7 @@
config SCHED_SMT
bool "SMT (Hyperthreading) scheduler support"
- depends on SMP
+ depends on X86_HT
help
SMT scheduler support improves the CPU scheduler's decision making
when dealing with Intel Pentium 4 chips with HyperThreading at a
@@ -238,7 +238,7 @@
config SCHED_MC
bool "Multi-core scheduler support"
- depends on SMP
+ depends on X86_HT
default y
help
Multi-core scheduler support improves the CPU scheduler's decision
Index: linux-2.6/arch/i386/kernel/cpu/common.c
===================================================================
--- linux-2.6.orig/arch/i386/kernel/cpu/common.c 2006-06-26 10:43:10.000000000 -0500
+++ linux-2.6/arch/i386/kernel/cpu/common.c 2006-06-26 10:51:40.000000000 -0500
@@ -294,7 +294,7 @@
if (c->x86 >= 0x6)
c->x86_model += ((tfms >> 16) & 0xF) << 4;
c->x86_mask = tfms & 15;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
#else
c->apicid = (ebx >> 24) & 0xFF;
Index: linux-2.6/arch/i386/kernel/cpu/intel_cacheinfo.c
===================================================================
--- linux-2.6.orig/arch/i386/kernel/cpu/intel_cacheinfo.c 2006-06-26 10:43:10.000000000 -0500
+++ linux-2.6/arch/i386/kernel/cpu/intel_cacheinfo.c 2006-06-26 10:51:40.000000000 -0500
@@ -174,7 +174,7 @@
unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
#endif
@@ -296,14 +296,14 @@
if (new_l2) {
l2 = new_l2;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
cpu_llc_id[cpu] = l2_id;
#endif
}
if (new_l3) {
l3 = new_l3;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
cpu_llc_id[cpu] = l3_id;
#endif
}
-
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