On Fri, 2006-06-23 at 08:56 -0500, Steve Wise wrote:
> On Fri, 2006-06-23 at 15:48 +0200, Arjan van de Ven wrote:
> > > > > + /* Tell HW to xmit */
> > > > > + __raw_writeq(cpu_to_be64(mapaddr), elem->hw_desc + C2_TXP_ADDR);
> > > > > + __raw_writew(cpu_to_be16(maplen), elem->hw_desc + C2_TXP_LEN);
> > > > > + __raw_writew(cpu_to_be16(TXP_HTXD_READY), elem->hw_desc + C2_TXP_FLAGS);
> > > >
> > > > or here
> > > >
> > >
> > > No need here. This logic submits the packet for transmission. We don't
> > > assume it is transmitted until we (after a completion interrupt usually)
> > > read back the HTXD entry and see the TXP_HTXD_DONE bit set (see
> > > c2_tx_interrupt()).
> >
> > ... but will that interrupt happen at all if these 3 writes never hit
> > the hardware?
> >
>
> I thought the posted write WILL eventually get to adapter memory. Not
> stall forever cached in a bridge. I'm wrong?
I'm not sure there is a theoretical upper bound....
(and if it's several msec per bridge, then you have a lot of latency
anyway)
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