On Wed, 21 Jun 2006 11:20:55 +0400 Kirill Smelkov wrote:
> Thanks for excellent article!
> While reading it I discovered a few typos.
>
> Signed-off-by: Kirill Smelkov <[email protected]>
>
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index 4710845..638b686 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -282,7 +282,7 @@ Memory barriers come in four basic varie
> A write barrier is a partial ordering on stores only; it is not required
> to have any effect on loads.
>
> - A CPU can be viewed as as commiting a sequence of store operations to the
> + A CPU can be viewed as commiting a sequence of store operations to the
committing
> memory system as time progresses. All stores before a write barrier will
> occur in the sequence _before_ all the stores after the write barrier.
>
---
~Randy
-
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