On Fri, 16 Jun 2006, Andi Kleen wrote:
> I don't think such a beast exists so far. So from that
> angle it doesn't help.
Hmmm.. Seemed to me that the L1 cacheline size is 64 byte on i386 at least
for some modern cpus but then I am not that familiar with i386.
config X86_L1_CACHE_SHIFT
int
default "7" if MPENTIUM4 || X86_GENERIC
default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
default "6" if MK7 || MK8 || MPENTIUMM
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