Re: [PATCHSET] block: fix PIO cache coherency bug, take 2

On Mon, Jun 05, 2006 at 11:16:42AM -0500, James Bottomley wrote:
> On Mon, 2006-06-05 at 16:48 +0100, Russell King wrote:
> > When does the zero copy case occur?
> 
> Almost all user initiated I/O.  Glibc tends to implement this as mmap
> internally.

Ah, so you _are_ talking about something different from what I'm
talking about.  I'm concentrating _solely_ on the _read_ side,
and all my responses so far have been concerned about that only.

Anyway, I think this discussion has become meaningless since we've
been talking at cross purposes for the entire thread.

-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 Serial core
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---

• References:
  • [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Tejun Heo <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Russell King <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Russell King <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: James Bottomley <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Russell King <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: James Bottomley <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Russell King <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: James Bottomley <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: Russell King <[email protected]>
  • Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
    • From: James Bottomley <[email protected]>

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