David S. Miller writes:
> From: Richard Henderson <[email protected]>
> Date: Wed, 10 May 2006 08:47:13 -0700
>
> > How do you plan to address the compiler optimizing
> ...
> > Across the schedule, we may have changed cpus, making the cached
> > address invalid.
>
> Per-cpu variables need to be accessed only with preemption
> disabled. And the preemption enable/disable operations
> provide a compiler memory barrier.
No, Richard has a point, it's not the value that is the concern, it's
the address, which gcc could assume is still valid after a barrier.
Drat.
Paul.
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