Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case

On Fri, 28 Apr 2006, Andi Kleen wrote:
> > 
> > I must be confused.  Doesn't that become a barrier() on UP?
> 
> No it was me who was confused sorry. Somehow i thought it was defined
> away for !SMP
> 
> (which would make sense because why would you want a compile barrier
> for a barrier that is only needed on SMP?) 

If the write barrier is needed on SMP, then UP needs a compiler barrier. 
Even UP has interrupts (and preemption) that can expose ordering of the 
interrupted code.

		Linus
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---

• References:
  • Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
    • From: Andi Kleen <[email protected]>
  • Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
    • From: Chris Wright <[email protected]>
  • Re: [PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
    • From: Andi Kleen <[email protected]>

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