> I don't see quite why it would do it (yes, ROM's are prefetchable, but the
> old location was _valid_, and I don't see why we didn't re-use it), but it
> _really_ shouldn't matter.
>
> I would expect some silly interaction with X, as usual. It would be nice
> to see the whole dmesg, especially with the debugging messages - I suspect
> the remapping of the ROM happens only when X starts up, and that your
> dmesg is from just the kernel boot from before that?
>
> But it might be that I just missed it (or that we don't have good debug
> output for that case).
Just on my own system I'm seeing something of an issue while debugging
the dual-head issue,
my secondary head is being assigned non-prefetchable resources outside
the bridge,
PCI: Transparent bridge - 0000:00:1e.0
PCI: Bridge: 0000:00:1e.0
IO window: b000-bfff
MEM window: ff900000-ff9fffff
PREFETCH window: e8000000-efffffff
is the bridge,
02:02.0 VGA compatible controller: ATI Technologies Inc Radeon RV100
QY [Radeon 7000/VE] (prog-if 00 [VGA])
Subsystem: C.P. Technology Co. Ltd: Unknown device 2049
Flags: stepping, medium devsel, IRQ 255
Memory at e8000000 (32-bit, prefetchable) [disabled] [size=128M]
I/O ports at b000 [disabled] [size=256]
Memory at ffff0000 (32-bit, non-prefetchable) [disabled] [size=64K]
Expansion ROM at ff900000 [disabled] [size=128K]
Capabilities: [50] Power Management version 2
is the device,
when I modprobe radeon which does pci_enable_device, the bars are enabled...
However when X starts it tries to reassign the memory at 0xffff0000
down into the bridge memory... at 0xfff90000, should the kernel do
this? or does it actually matter if the memory is behind the bridge as
its transparent... maybe I can at least patch X to check for
transparent bridges...
Dave.
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