Thats right. This will be made a non issue with early demuxing
on the NIC and MSI (or was it MSI-X?) which will select
the right CPU based on hardware channels.
MSI-X. with MSI you still have only one cpu handling all MSI interrupts and
that doesn't look any different than ordinary interrupts. MSI-X will allow
much better interrupt handling across several cpu's.
Auke
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Message signaled interrupts are just a kudge to save a trace on a
PC board (read make junk cheaper still). They are not faster and
may even be slower. They will not be the salvation of any interrupt
latency problems. The solutions for increasing networking speed,
where the bit-rate on the wire gets close to the bit-rate on the
bus, is to put more and more of the networking code inside the
network board. The CPU get interrupted after most things (like
network handshakes) are complete.
if the issue is bus vs network bitrates would offloading really buy that
much? i suppose that for minimum sized packets not DMA'ing the headers
across the bus would be a decent win, but down at small packet sizes
where headers would be 1/3 to 1/2 the stuff DMA'd around, I would think
one is talking more about CPU path lengths than bus bitrates.
and up and "full size" segments, since everyone is so fond of bulk
transfer tests, the transfer saved by not shovig headers across the bus
is what 54/1448 or ~3.75%
spreading interrupts via MSI-X seems nice and all, but i keep wondering
if the header field-based distribution that is (will be) done by the
NICs is putting the cart before the horse - should the NIC essentially
be telling the system the CPU on which to run the application, or should
the CPU on which the application runs be telling "networking" where it
should be happening?
rick jones
-
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