Neil Brown wrote:
However there is room for a race here. If an event occurs between
the read and the write, then this will NOT de-assert the IRQ line.
It will remain asserted throughout.
Now if the IRQ is handled as an edge-triggered line (which I believe
they are in Linux), then losing this race will mean that we don't see
any more interrupts on this line.
PCI interrupts should always be level triggered, not edge triggered
(except maybe in a few special cases - non-native-mode PCI IDE maybe?
and in those cases I don't think the interrupt is considered sharable).
With a level triggered interrupt the ISR will simply be triggered again
and the event handled in this case so there is no race. I think this
patch is going to double interrupt overhead and only covers up some
other problem.
I think that in cases where the interrupt is edge triggered and is
shared (for example on ISA cards that support it) the kernel already has
such logic as you describe.
--
Robert Hancock Saskatoon, SK, Canada
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Home Page: http://www.roberthancock.com/
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