On Iau, 2006-03-09 at 08:49 +1100, Paul Mackerras wrote:
> If the device accesses to memory are in response to an MMIO store,
> then the code needs an explicit wmb() between the memory stores and
> the MMIO store. Disabling interrupts isn't going to help here because
> the device doesn't see the CPU interrupt enable state.
Interrupts are themselves entirely asynchronous anyway. The following
can occur on SMP Pentium-PIII.
Device
Raise IRQ
CPU
writel(MASK_IRQ, &dev->ctrl);
readl(&dev->ctrl);
IRQ arrives
CPU specific IRQ masking is synchronous, but IRQ delivery is not,
including IPI delivery (which is asynchronous and not guaranteed to
occur only once per IPI but can be replayed in obscure cases on x86).
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