On Mer, 2006-03-08 at 20:16 +0000, David Howells wrote:
> The LOCK and UNLOCK functions presumably make at least one memory write apiece
> to manipulate the target lock (on SMP at least).
No they merely perform the bus transactions neccessary to perform an
update atomically. They are however "serializing" instructions which
means they do cause a certain amount of serialization (see the intel
architecture manual on serializing instructions for detail).
Athlon and later know how to turn it from locked memory accesses into
merely an exclusive cache line grab.
> > This makes it sound like pentium-III+ is incompatible with previous
> > CPUs. Is it really the case?
>
> Yes - hence the alternative instruction stuff.
It is the case for certain specialist instructions and the fences are
provided to go with those but can also help in other cases. PIII and
later in particular support explicit non temporal stores.
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