On Tue, 7 Mar 2006, Alan Cox wrote:
>
> In the PCI case the I/O write appears to be acked by the bridges used on
> x86 when the write completes on the PCI bus and then back to the CPU.
> MMIO is thankfully posted. At least thats how the timings on some
> devices look.
Oh, absolutely. I'm sayign that you shouldn't wait for even that, since
it's totally pointless (it's not synchronized _anyway_) and adds
absolutely zero gain. To really synchronize, you need to read from the
device anyway.
So the "wait for bus activity" is just making PIO slower for no good
reason, and keeps the core waiting when it could do something more useful.
On an x86, there are legacy reasons to do it (people expect certain
timings). But that was what I was saying - on non-x86 architectures,
there's no reason for the ioread/iowrite interfaces to be as serializing
as the old-fashioned PIO ones are. Might as well do the MMIO rules for a
non-cacheable region: no re-ordering, but no waiting for the bus either.
Linus
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