On Wed, 2006-03-01 at 20:49 +0100, Andi Kleen wrote:
> Relying on undocumented side effects of instructions as you're trying
> to do here is not very reliable and would likely cause breakage later.
I just quoted you the precise relevant semantics of sfence two messages
earlier, from the AMD64 optimisation guide. Here's the same thing from
the EM64T optimisation guide. See page 444 of the following PDF:
ftp://download.intel.com/design/Pentium4/manuals/25366818.pdf
Here's the relevant quote:
Writes may be delayed and combined in the write combining buffer
(WC buffer) to reduce memory accesses. If the WC buffer is
partially filled, the writes may be delayed until the next
occurrence of a serializing event; such as, an SFENCE or MFENCE
instruction, [...]
If you read section 10.3.1 of the same document (page 446), you'll see
that a CLFLUSH (as you suggested earlier) won't even work to get the WC
buffers to flush, because they're not part of the regular cache
hierarchy.
This section also makes it clear yet again that wmb() is absolutely not
sufficient to get program store order semantics in the presence of WC;
you *have* to use an explicit synchronising instruction of some kind.
This is pretty frustrating. I'm quoting the manufacturer documentation
at you, and you're handwaving back at me with complete nonsense.
<b
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