On Sat, 2006-02-25 at 12:41 -0500, Benjamin LaHaise wrote:
> That is not the same as saying the write buffers are flushed and wholly
> visible to their destination, it just means that subsequent reads or
> writes will not be reordered prior to the sfence instruction.
Right. I don't need the writes to be visible at the destination device,
in this particular case; a write followed by a barrier just has to show
up at the device before the next write.
Here's what a write to our chip looks like, for sending a packet:
* write a 64-bit control register that includes the length of the
segment being written
* do a barrier to make sure it gets to the device before any other
writes
* perform a pile of writes using __iowrite_copy32, not caring
about the order in which they reach the chip
* do another barrier
* perform one final 32-bit write using __raw_writel
* do one final barrier
The last 32-bit write triggers the chip to put the packet on the wire.
We make sure it happens after the earlier bulk write using a barrier.
<b
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