On Tue, Feb 07, 2006 at 02:54:43PM -0800, Gabriele Gorla wrote:
> Set the cache line size in the PCI configuration space to a reasonable
> value. SRM does not seem to set this register for the PCI cards that it
> does not recognize. This makes drivers that expect cache line size to be
> set by the card bios work on alpha.
I don't see such drivers in the mainline.
Anyhow, the PCI_CACHE_LINE_SIZE setting is critical only for devices
that do memory-write-invalidate. In this case a driver must call
pci_set_mwi() which takes care of PCI_CACHE_LINE_SIZE.
The patch is NAKed.
Ivan.
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