On Tue, 2006-02-07 at 11:50 +0000, David Vrabel wrote:
> PXA27x has a clock speed of 13000000 Hz.
>
Yea... And this affects the divisor calculation depending on type of CPU
and when the CPU is a PXA260 or PXA25x which SSP port. And worse, the
SSP controller (as opposed to the NSSP/ASSP) on the PXA25x and PXA260
use a different divisor calculation:
Serial Bit Rate = SSP Port Clock / 2 / (SCR + 1)
The pxa_regs.h file is misleading and potentially inaccurate in this
respect.
> Consider spi->max_speed_hz == CLOCK_SPEED_HZ which gives a divisor of 3
> (when it should be 1).
>
> You need SSCR0_SerClkDiv(CLOCK_SPEED_HZ / (spi->max_speed_hz + 1) + 1)
> for the correct divisor and for proper rounding.
Yes, but see qualification above. I will fix this as you suggest, with
some modifications. FYI The CPU differences also exposed a similar
problem with the DMA setup. Thanks!
>
> > + /* Attach to IRQ */
> > + irq = platform_get_irq(pdev, 0);
> > + if (irq == 0) {
> > + dev_err(&pdev->dev, "irq resource not defined\n");
> > + status = -ENODEV;
> > + goto out_error_master_alloc;
> > + }
>
> Greg K-H has a patch pending that makes platform_get_irq() return -ENXIO
> instead of 0 on error. This is required for SSP3 on the PXA27x which
> uses IRQ 0.
>
> > + /* Release IRQ */
> > + irq = platform_get_irq(pdev, 0);
> > + if (irq != 0)
> > + free_irq(irq, drv_data);
>
> Similarly.
Will do.
I will re-post the patch again to today. Thanks for the help.
-Stephen
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