RE: [PATCH] amd76x_pm: C3 powersaving for AMD K7

["Brown, Len" <len.brown@intel.com>]

>... I disagree with Len in two points:
>- I cannot see a problem witch cache snooping.
>  The AMD-768 docs clearly
>  states that trying to snoop the cache while in C3 is a resume event.

Certainly the BIOS writer also had access to that document, plus
documents we do not see, yet they decided NOT to enable C2/C3.

>- Enabling C2/C3 in the BIOS would be a very bad thing IMHO.
>  From all he testing with amd76x_pm I found that is very tricky
>  to go into C2/C3 "the right way".

Who defines the "right way"?  Is it guaranteed to work on all
models and all configurations?  Exactly what is the reward
for the cost we'd be paying and the risk we'd be taking?

>  Simply reading the PM register without a
>  suitable logic around leads to all kinds of instabilities.  You need
>  to implement this logic and then enable the hardware.  The BIOS cannot
>  do this.

How about if we put it this way...
If the ACPI maintainer were an AMD employee,
and he accepted a patch like this specific to Intel hardware --
a patch that rejects whatever validation Intel, the BIOS
vendor and the board vendor have put into the product --
I'd call for his expulsion for ineptitude.

If somebody from AMD steps forth and says that hey, their hardware
is broken if used in the standard way, but that this "logic around"
is a valid model-specific workaround -- then we have something
that MAYBE we can work with.  Otherwise, do whatever works for your
own system, but it would be reckless of us to put stuff like this
in the upstream kernel and then ask distros to support it.

-Len
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