[PCI] Optional pre-fetchable memory registers

["Jordan Crouse" <jordan.crouse@amd.com>]

I've been going back and forth with one of my BIOS guys for a while, 
and I need some clarity on a decision in the PCI probe code...

According to the PCI-to-PCI bridge spec (v1.1), the prefetchable memory base
register and prefetchable memory limit registers are optional, and if
the bridge does not implement a prefetchable memory address range, then the
registers must be implemented as read-only registers which return zero
when read [1].

So, as far as I can tell, drivers/pci/probe.c:312 assumes if
base <= limit (which it would, if both returned zero), then it will go 
ahead and set up the region (line 313-315), which
would cause pcibios_allocate_bus_resources in i386.c to allocate the region, 
and print a nice little error message when base turned out to be zero.  
Now, the end result is the same (area disabled), but it would seem that 
we could avoid any grief at all by assuming that 0x0 for base on 
probe.c:312 means that the prefetchable region doesn't exist.

Or am I barking up the wrong tree?

Regards,
Jordan

[1] Section 3.2.5.9

-- 
Jordan Crouse
Senior Linux Engineer
AMD - Personal Connectivity Solutions Group
<www.amd.com/embeddedprocessors>

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