On Thu, 2006-01-12 at 22:18 -0500, Steven Rostedt wrote: > OK, I'm actually sending you this email on a x86_64 running > 2.6.15-rt4-sr2, with latency tracing on. But unfortunately, I have a > AMD X2 that each core has it's own tsc counter that is not in sync, and > since the latency tracer uses tsc, I get garbage. But beware, the tsc > does slow down when the cpu idles, so it gives bad results even for non > x2 systems. > Hmm, I didn't realize that (I'm running on a uni-processor system). I just pulled your rt4-sr2 patch and will apply/rebuild/test. > I finally was able to boot this with using the PM timer, but the > beginning of my dmesg is still filled with: > > read_tsc: ACK! TSC went backward! Unsynced TSCs? > > Have you tried booting with idle=poll? I wonder if that would help? No, I thought that was strictly an SMP issue. I'll try it as well. Thanks, Clark -- Clark Williams <[email protected]>
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